View FSQ0765RS_28166.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
March 2010
FSQ0765RS Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation - Low EMI and High Efficiency
Features
! Optimized for Quasi-Resonant Converter (QRC) ! Low EMI through Variable Frequency Control and AVS
Description
A Quasi-Resonant Converter (QRC) generally shows lower EMI and higher power conversion efficiency than a conventional hard-switched converter with a fixed switching frequency. The FSQ-series is an integrated Pulse-Width Modulation (PWM) controller and SenseFET specifically designed for quasi-resonant operation and Alternating Valley Switching (AVS). The PWM controller includes an integrated fixed-frequency oscillator, Under-Voltage Lockout (UVLO), LeadingEdge Blanking (LEB), optimized gate driver, internal softstart, temperature-compensated precise current sources for a loop compensation, and self-protection circuitry. Compared with a discrete MOSFET and PWM controller solution, the FSQ-series can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. This device provides a basic platform for cost-effective designs of quasi-resonant switching flyback converters.
(Alternating Valley Switching)
! High Efficiency through Minimum Voltage Switching ! Narrow Frequency Variation Range over Wide Load
and Input Voltage Variation Power Consumption
! Advanced Burst-Mode Operation for Low Standby ! Simple Scheme for Sync-Voltage Detection ! Pulse-by-Pulse Current Limit ! Various Protection functions: Overload Protection
! ! ! !
(OLP), Over-Voltage Protection (OVP), Abnormal Over-Current Protection (AOCP), Internal Thermal Shutdown (TSD) with Hysteresis, Output Short Protection (OSP) Under-Voltage Lockout (UVLO) with Hysteresis Internal Startup Circuit Internal High-Voltage Sense FET (650V) Built-in Soft-Start (17.5ms)
Applications
! Power Supply for LCD TV and Monitor, VCR, SVR,
STB, and DVD & DVD Recorder
! Adapter
Related Resources
Visit: http://www.fairchildsemi.com/apnotes/ for:
! AN-4134: Design Guidelines for Off-line Forward ! !
! ! ! ! !
Converters Using Fairchild Power Switch (FPSTM) AN-4137: Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPSTM) AN-4140: Transformer Design Consideration for off-line Flyback Converters using Fairchild Power Switch (FPSTM) AN-4141: Troubleshooting and Design Tips for Fairchild Power Switch (FPSTM) Flyback Applications AN-4145: Electromagnetic Compatibility for Power Converters AN-4147: Design Guidelines for RCD Snubber of Flyback Converters AN-4148: Audible Noise Reduction Techniques for FPS Applications AN-4150: Design Guidelines for Flyback Converters Using FSQ-series Fairchild Power Switch (FPSTM)
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Ordering Information
Maximum Output Power(1) Product Number PKG.(5) Operating Temp. Current RDS(ON) Limit Max. 230VAC15%(2) Adapter(3)
80W
85-265VAC
Open Open Adapter(3) Frame(4) Frame(4)
90W 48W 70W
Replaces Devices
FSCM0765R FSDM07652RE
FSQ0765RSWDTU TO-220F-6L -25 to +85C
2.5A
1.6
Notes: 1. The junction temperature can limit the maximum output power. 2. 230VAC or 100/115VAC with doubler. 3. Typical continuous power in a non-ventilated enclosed adapter measured at 50C ambient temperature. 4. Maximum practical continuous power in an open-frame design at 50C ambient.
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 2
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Application Diagram
VO
AC IN Vstr PWM FB VCC Drain
Sync
GND
FSQ0765R Rev.00
Figure 1. Typical Flyback Application
Internal Block Diagram
Sync 5 Vstr 6 VCC 3 Drain 1
AVS
0.35/0.55 VBurst IFB 3R R tON < tOSP after SS SoftStart PWM
OSC VCC Vref VCC good 8V/12V
VCC
Vref Idelay
FB 4
SQ LEB 250ns RQ Gate driver
VOSP
LPF AOCP
VSD VCC VOVP LPF
TSD
S
Q
2
VOCP (1.1V)
GND
RQ
VCC good FSQ0765RS Rev.00
Figure 2. Internal Block Diagram
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 3
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Pin Configuration
6. Vstr 5. Sync 4. FB 3. VCC 2. GND 1. Drain
FSQ0765R Rev.00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
1 2 3
Name
Drain GND VCC
Description
SenseFET drain. High-voltage power SenseFET drain connection. Ground. This pin is the control ground and the SenseFET source. Power Supply. This pin is the positive supply input, providing internal operating current for both startup and steady-state operation. Feedback. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. If the voltage of this pin reaches 6V, the overload protection triggers, which shuts down the FPS. Sync. This pin is internally connected to the sync-detect comparator for quasi-resonant switching. In normal quasi-resonant operation, the threshold of the sync comparator is 1.2V/1.0V. Startup. This pin is connected directly, or through a resistor, to the high-voltage DC link. At startup, the internal high-voltage current source supplies internal bias and charges the external capacitor connected to the VCC pin. Once VCC reaches 12V, the internal current source is disabled. It is not recommended to connect Vstr and Drain together.
4
FB
5
Sync
6
Vstr
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 4
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA = 25C, unless otherwise specified.
Symbol
Vstr VDS VCC VFB VSync IDM ID EAS PD TJ TA TSTG ESD Vstr Pin Voltage Drain Pin Voltage Supply Voltage
Parameter
Min.
500 650
Max.
Unit
V V
20 -0.3 -0.3 TC = 25C TC = 100C VCC
(5)
V V V A A mJ W C C C kV kV
Feedback Voltage Range Sync Pin Voltage Drain Current Pulsed Continuous Drain Current(6) Single Pulsed Avalanche Energy(7) Total Power Dissipation (TC=25C) Operating Junction Temperature Operating Ambient Temperature Storage Temperature Electrostatic Discharge Protection Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101
13.0 14.4 3.60 2.28 570 45
Internally limited -25 -55 2.0 2.0 +85 +150
Notes: 5. Guarenteed when external current applied to FB pin is lower than 100A. 6. Repetitive rating: Pulse-width limited by maximum junction temperature. 7. L=81mH, starting TJ=25C.
Thermal Impedance
TA = 25C unless otherwise specified.
Symbol
JA JC
Parameter
Junction-to-Ambient Thermal Resistance(8) Junction-to-Case Thermal Resistance(9)
Package
TO-220F-6L
Value
50 2.8
Unit
C/W C/W
Notes: 8. Free standing with no heat-sink under natural convection. 9. Infinite cooling condition - refer to the SEMI G30-88.
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 5
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Electrical Characteristics
TA = 25C unless otherwise specified.
Symbol
SENSEFET SECTION
BVDSS IDSS RDS(ON) COSS td(on) tr td(off) tf tON.MAX tB tW fSW fSW tAVS VAVS tSW IFB DMIN VSTART VSTOP tS/S VOVP VBURH VBURL VB_HYS
Parameter
Drain Source Breakdown Voltage Zero-Gate-Voltage Drain Current Drain-Source On-State Resistance Output Capacitance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Maximum On Time Blanking Time Detection Time Window Initial Switching Frequency Switching Frequency Variation(11) AVS Triggering Threshold(11) On Time Feedback Voltage
Conditions
VCC = 0V, ID = 100A VDS = 520V, VGS = 0V TJ = 25C, ID = 1.8A VGS = 0V, VDS = 25V, f = 1MHz
Min.
650
Typ. Max. Units
V 300 1.3 125 27 102 63 65 1.6 A pF ns ns ns ns 11.2 16.8 75.8 10 s s s kHz % s V 20.5 900 12 8 17.5 19 0.55 0.35 200 1100 0 13 9 20 0.65 0.45 s A % V V ms V V V mV
VDD = 325V, ID = 6.5A
CONTROL SECTION
TJ = 25C TJ = 25C, Vsync = 5V TJ = 25C, Vsync = 0V 59.6 -25C < TJ < 85C at VIN = 240VDC, Lm = 360H (AVS triggered when VAVS>spec & tAVS(10)
8.8 13.2
10.0 15.0 6.0 66.7 5 4.0 1.2
Switching Time Variance by AVS(11) Feedback Source Current Minimum Duty Cycle UVLO Threshold Voltage Internal Soft-Start Time Over-Voltage Protection
13.5 700
7
BURST-MODE SECTION
0.25
Note: 10. Propagation delay in the control IC.
Continued on the following page...
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 6
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Electrical Characteristics (Continued)
TA = 25C unless otherwise specified.
Symbol
PROTECTION SECTION
ILIMIT VSD IDELAY tLEB tOSP VOSP tOSP_FB TSD Hys VSH1 VSL1 tsync VSH2 VSL2 VCLAMP
Parameter
Peak Current Limit Shutdown Feedback Voltage Shutdown Delay Current Leading-Edge Blanking Time(11) Threshold Time
Conditions
TJ = 25C, di/dt = 460mA/s VCC = 15V VFB = 5V
Min. Typ. Max. Units
2.20 5.5 4 2.50 6.0 5 250 1.2 1.8 2.0 125 2.0 2.5 140 60 1.0 0.8 4.3 4.0 0.0 1.2 1.0 230 4.7 4.4 0.4 1.4 1.2 5.1 4.8 0.8 3.0 155 1.4 2.80 6.5 6 A V A ns s V s C
Output Short Threshold Feedback Protection(11) Voltage
TJ = 25C OSP triggered when tONVOSP & lasts longer than Feedback Blanking Time tOSP_FB
Shutdown Temperature Thermal Shutdown(11) Hysteresis
SYNC SECTION
Sync Threshold Voltage 1 Sync Delay Time(11)(12) Sync Threshold Voltage 2 Low Clamp Voltage VCC = 15V, VFB = 2V ISYNC_MAX = 800A ISYNC_MIN = 50A VCC = 15V, VFB = 2V V ns V V
TOTAL DEVICE SECTION
IOP ISTART ICH VSTR Operating Supply Current (Control Part Only) Start Current Startup Charging Current Minimum VSTR Supply Voltage VCC = 13V VCC = 10V (before VCC reaches VSTART) VCC = 0V, VSTR = minimum 50V 1 350 0.65 3 450 0.85 26 5 550 1.00 mA A mA V
Notes: 11.Guaranteed by design, but not tested in production. 12. Includes gate turn-on time.
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 7
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Comparison Between FSDM0x65RNB and FSQ-Series
Function
Operation Method
FSDM0x65RE
Constant Frequency PWM Frequency Modulation
FSQ-Series
Quasi-Resonant Operation
FSQ-Series Advantages
! Improved efficiency by valley switching ! Reduced EMI noise ! Reduced components to detect valley point
EMI Reduction
! Valley switching Reduce EMI Noise ! Inherent frequency modulation ! Alternate valley switching
Hybrid Control Burst-Mode Operation Strong Protections TSD Burst-Mode Operation OLP, OVP 145C without Hysteresis
CCM or AVS Based on Load ! Improves efficiency by introducing hybrid control and Input Condition Advanced Burst-Mode Operation OLP, OVP, AOCP, OSP 140C with 60C Hysteresis
! Improved standby power by AVS in burst-mode ! Improved reliability through precise AOCP ! Improved reliability through precise OSP ! Stable and reliable TSD operation ! Converter temperature range
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 8
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Typical Performance Characteristics
These characteristic graphs are normalized at TA= 25C.
Normalized
1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Normalized
1.2
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Temperature [C]
Figure 13. Operating Supply Current (IOP) vs. TA
Temperature [C]
Figure 14. UVLO Start Threshold Voltage (VSTART) vs. TA
Normalized
1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Normalized
1.2
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Temperature [C]
Figure 15. UVLO Stop Threshold Voltage (VSTOP) vs. TA
Temperature [C]
Figure 16. Startup Charging Current (ICH) vs. TA
Normalized
1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Normalized
1.2
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Temperature [C]
Figure 17. Initial Switching Frequency (fSW) vs. TA
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 9
Temperature [C]
Figure 18. Maximum On Time (tON.MAX) vs. TA
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA= 25C.
Normalized
1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Normalized
1.2
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Temperature [C]
Figure 19. Blanking Time (tB) vs. TA
Temperature [C]
Figure 20. Feedback Source Current (IFB) vs. TA
Normalized
1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Normalized
1.2
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Temperature [C]
Figure 21. Shutdown Delay Current (IDELAY) vs. TA
Temperature [C]
Figure 22. Burst-Mode High Threshold Voltage (Vburh) vs. TA
Normalized
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Normalized
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Temperature [C]
Figure 23. Burst-Mode Low Threshold Voltage (Vburl) vs. TA
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 10
Temperature [C]
Figure 24. Peak Current Limit (ILIM) vs. TA
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Typical Performance Characteristics (Continued)
These characteristic graphs are normalized at TA= 25C.
Normalized
1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Normalized
1.2
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Temperature [C]
Figure 25. Sync High Threshold Voltage 1 (VSH1) vs. TA
Temperature [C]
Figure 26. Sync Low Threshold Voltage 1 (VSL1) vs. TA
Normalized
1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Normalized
1.2
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Temperature [C]
Figure 27. Shutdown Feedback Voltage (VSD) vs. TA
Temperature [C]
Figure 28. Over-Voltage Protection (VOV) vs. TA
Normalized
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Normalized
1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125
Temperature [C]
Figure 29. Sync High Threshold Voltage 2 (VSH2) vs. TA
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 11
Temperature [C]
Figure 30. Sync Low Threshold Voltage 2 (VSL2) vs. TA
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Functional Description
1. Startup: At startup, an internal high-voltage current source supplies the internal bias and charges the external capacitor (Ca) connected to the VCC pin, as illustrated in Figure 22. When VCC reaches 12V, the FPSTM begins switching and the internal high-voltage current source is disabled. The FPS continues its normal switching operation and the power is supplied from the auxiliary transformer winding unless VCC goes below the stop voltage of 8V.
VDC
2.1 Pulse-by-Pulse Current Limit: Because currentmode control is employed, the peak current through the SenseFET is limited by the inverting input of PWM comparator (VFB*), as shown in Figure 23. Assuming that the 0.9mA current source flows only through the internal resistor (3R + R = 2.8k), the cathode voltage of diode D2 is about 2.5V. Since D1 is blocked when the feedback voltage (VFB) exceeds 2.5V, the maximum voltage of the cathode of D2 is clamped at this voltage, clamping VFB*. Therefore, the peak value of the current through the SenseFET is limited. 2.2 Leading-Edge Blanking (LEB): At the instant the internal SenseFET is turned on, a high-current spike usually occurs through the SenseFET, caused by primary-side capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the Rsense resistor would lead to incorrect feedback operation in the current-mode PWM control. To counter this effect, the FPS employs a leading-edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (tLEB) after the SenseFET is turned on in the PulseWidth-Modulation (PWM) circuit. 3. Synchronization: The FSQ-series employs a quasiresonant switching technique to minimize the switching noise and loss. The basic waveforms of the quasiresonant converter are shown in Figure 24. To minimize the MOSFET's switching loss, the MOSFET should be turned on when the drain voltage reaches its minimum value, which is indirectly detected by monitoring the VCC winding voltage, as shown in Figure 24.
Vds
Ca
3
VCC
6 ICH
Vstr
8V/12V
VCC good
Vref
FSQ0765R Rev.00
Internal Bias
Figure 31. Startup Circuit 2. Feedback Control: FPS employs current-mode control, as shown in Figure 23. An opto-coupler (such as the FOD817A) and shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor makes it possible to control the switching duty cycle. When the reference pin voltage of the shunt regulator exceeds the internal reference voltage of 2.5V, the opto-coupler LED current increases, pulling down the feedback voltage and reducing the duty cycle. This typically happens when the input voltage is increased or the output load is decreased.
VCC Idelay Vref IFB
OSC
VRO VRO
VDC
Vsync
tF Vovp (8V)
VO
FOD817A
VFB
CB
1.2V
SenseFET
4 D1 D2 + VFB* R 3R
1.0V 230ns Delay
Gate driver
MOSFET Gate
KA431
-
ON
ON
VSD
FSQ0765R Rev. 00
OLP
Rsense
FSQ0765R Rev.00
Figure 32. Pulse-Width-Modulation (PWM) Circuit
Figure 33. Quasi-Resonant Switching Waveforms
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 12
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
The switching frequency is the combination of blank time (tB) and detection time window (tW). In case of a heavy load, the sync voltage remains flat after tB and waits for valley detection during tW. This leads to a low switching frequency not suitable for heavy loads. To correct this drawback, additional timing is used. The timing conditions are described in Figures 25, 26, and 27. When the Vsync remains flat higher than 4.4V at the end of tB which is instant tX, the next switching cycle starts after internal delay time from tX. In the second case, the next switching occurs on the valley when the Vsync goes below 4.4V within tB. Once Vsync detects the first valley in tB, the other switching cycle follows classical QRC operation.
tB=15s
tX
IDS
IDS
VDS ingnore
4.4V
Vsync
1.2V 1.0V
tB=15s
tX
internal delay
FSQ0765R Rev. 00
Figure 36. After Vsync Finds First Valley
IDS IDS
VDS
4.4V
Vsync
1.2V 1.0V
internal delay
FSQ0765R Rev. 00
Figure 34. Vsync > 4.4V at tX
tB=15s tX
4. Protection Circuits: The FSQ-series has several self-protective functions, such as Overload Protection (OLP), Abnormal Over-Current Protection (AOCP), Over-Voltage Protection (OVP), and Thermal Shutdown (TSD). All the protections are implemented as autorestart mode. Once the fault condition is detected, switching is terminated and the SenseFET remains off. This causes VCC to fall. When VCC falls down to the Under-Voltage Lockout (UVLO) stop voltage of 8V, the protection is reset and the startup circuit charges the VCC capacitor. When the VCC reaches the start voltage of 12V, normal operation resumes. If the fault condition is not removed, the SenseFET remains off and VCC drops to stop voltage again. In this manner, the auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated. Because these protection circuits are fully integrated into the IC without external components, the reliability is improved without increasing cost.
VDS
Power on Fault occurs Fault removed
IDS
IDS
VDS
VCC
4.4V
Vsync
12V 8V
1.2V 1.0V
internal delay
FSQ0765R Rev. 00
FSQ0765R Rev. 00
Normal operation
Fault situation
Normal operation
t
Figure 35. Vsync < 4.4V at tX
Figure 37. Auto-Restart Protection Waveforms
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 13
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
AOCP FSQ0765R Rev.00
Figure 39. Abnormal Over-Current Protection
4.3 Output-Short Protection (OSP): If the output is shorted, steep current with extremely high di/dt can flow through the SenseFET during the LEB time. Such a steep current brings high voltage stress on drain of SenseFET when turned off. To protect the device from such an abnormal condition, OSP is included in the FSQseries. It is comprised of detecting VFB and SenseFET turn-on time. When the VFB is higher than 2V and the SenseFET turn-on time is lower than 1.2s, the FPS recognizes this condition as an abnormal error and shuts down PWM switching until VCC reaches Vstart again. An abnormal condition output short is shown in Figure 31.
MOSFET Drain Current Rectifier Diode Current Turn-off delay
VFB
6.0V
FSQ0765R Rev.00
Overload protection
V FB
0
2.5V t12= CFB*(6.0-2.5)/Idelay
Vo
D
Minimum turn-on time 1.2 s
output short occurs
0
t1
t2
t
Io
FSQ0765R Rev. 00
Figure 38. Overload Protection 4.2 Abnormal Over-Current Protection (AOCP): When the secondary rectifier diodes or the transformer pins are shorted, a steep current with extremely high di/dt can flow through the SenseFET during the LEB time. Even though the FSQ-series has overload protection, it is not enough to protect the FSQ-series in that abnormal case, since severe current stress is imposed on the SenseFET until OLP triggers. The FSQ-series has an internal AOCP circuit shown in Figure 30. When the gate turn-on signal is applied to the power SenseFET, the AOCP block is enabled and monitors the current through the sensing resistor. The voltage across the resistor is compared with a preset AOCP level. If the sensing resistor voltage is greater than the AOCP level, the set signal is applied to the latch, resulting in the shutdown of the SMPS.
0
Figure 40. Output Short Waveforms 4.4 Over-Voltage Protection (OVP): If the secondaryside feedback circuit malfunctions or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. Then, VFB climbs up in a similar manner to the overload situation, forcing the preset maximum current to be supplied to the SMPS until overload protection is activated. Because more energy than required is provided to the output, the output voltage may exceed the rated voltage before overload protection is activated, resulting in the breakdown of the devices in the secondary side. To prevent this situation, an over-voltage protection (OVP) circuit is employed. In general, VCC is proportional to the output voltage and the FSQ-series
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 14
+
-
4.1 Overload Protection (OLP): Overload is defined as the load current exceeding its normal level due to an unexpected abnormal event. In this situation, the protection circuit should trigger to protect the SMPS. However, even when the SMPS is in the normal operation, the overload protection circuit can be triggered during the load transition. To avoid this undesired operation, the overload protection circuit is designed to trigger only after a specified time to determine whether it is a transient situation or a true overload situation. Because of the pulse-by-pulse current limit capability, the maximum peak current through the SenseFET is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes more than this maximum power, the output voltage (VO) decreases below the set voltage. This reduces the current through the optocoupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (VFB). If VFB exceeds 2.5V, D1 is blocked and the 5A current source starts to charge CB slowly up to VCC. In this condition, VFB continues increasing until it reaches 6V, when the switching operation is terminated, as shown in Figure 29. The delay time for shutdown is the time required to charge CFB from 2.5V to 6V with 5A. A 20 ~ 50ms delay time is typical for most applications.
3R
OSC PWM LEB 250ns
S R Q Q
Gate driver
R
R sense VOCP
2 GND
ILIM
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
uses VCC instead of directly monitoring the output voltage. If VCC exceeds 19V, an OVP circuit is activated resulting in the termination of the switching operation. To avoid undesired activation of OVP during normal operation, VCC should be designed to be below 19V.
VO
VOset
VFB
0.55V 0.35V
4.5 Thermal Shutdown with Hysteresis (TSD): The SenseFET and the control IC are built in one package. This enables the control IC to detect the abnormally high temperature of the SenseFET. If the temperature exceeds approximately 140C, the thermal shutdown triggers IC shutdown. The IC recovers its operation when the junction temperature decreases 60C from TSD temperature and VCC reaches startup voltage (Vstart). 5. Soft-Start: The FPS has an internal soft-start circuit that increases PWM comparator inverting input voltage with the SenseFET current slowly after it starts up. The typical soft-start time is 17.5ms. The pulse width to the power-switching device is progressively increased to establish the correct working conditions for transformers, inductors, and capacitors. The voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. This mode helps prevent transformer saturation and reduces stress on the secondary diode during startup. 6. Burst Operation: To minimize power dissipation in standby mode, the FPS enters burst-mode operation. As the load decreases, the feedback voltage decreases. As shown in Figure 32, the device automatically enters burst-mode when the feedback voltage drops below VBURL (350mV). At this point, switching stops and the output voltages start to drop at a rate dependent on standby current load. This causes the feedback voltage to rise. Once it passes VBURH (550mV), switching resumes. The feedback voltage then falls and the process repeats. Burst-mode operation alternately enables and disables switching of the power SenseFET, thereby reducing switching loss in standby mode.
IDS
VDS
time
FSQ0765R Rev.00
t1
Switching disabled
t2 t3
Switching disabled
t4
Figure 41. Waveforms of Burst Operation 7. Switching Frequency Limit: To minimize switching loss and Electromagnetic Interference (EMI), the MOSFET turns on when the drain voltage reaches its minimum value in quasi-resonant operation. However, this causes switching-frequency to increases at lightload conditions. As the load decreases or input voltage increases, the peak drain current diminishes and the switching frequency increases. This results in severe switching losses at light-load condition, as well as intermittent switching and audible noise. These problems create limitations for the quasi-resonant converter topology in a wide range of applications.
To overcome these problems, FSQ-series employs a frequency-limit function, as shown in Figures 34 and 35. Once the SenseFET is turned on, the next turn-on is prohibited during the blanking time (tB). After the blanking time, the controller finds the valley within the detection time window (tW) and turns on the MOSFET, as shown in Figures 33 and Figure 34 (Cases A, B, and C). If no valley is found during tW, the internal SenseFET is forced to turn on at the end of tW (Case D). Therefore, the devices have a minimum switching frequency of 48kHz and a maximum switching frequency of 67kHz.
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 15
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
IDS
tsmax=21s
IDS A
tB=15s ts IDS IDS
8. AVS (Alternating Valley Switching): Due to the quasi-resonant operation with limited frequency, the switching frequency varies depending on input voltage, load transition, and so on. At high input voltage, the switching on time is relatively small compared to low input voltage. The input voltage variance is small and the switching-frequency modulation width becomes small. To improve the EMI performance, AVS is enabled when input voltage is high and the switching on time is small.
Internally, quasi-resonant operation is divided into two categories; one is first valley switching and the other is second-valley switching after blanking time. In AVS, two successive occurrences of first-valley switching and the other two successive occurrences of second-valley switching is alternatively selected to maximize frequency modulation. As depicted in Figure 34, the switching frequency hops when the input voltage is high. The internal timing diagram of AVS is described in Figure 35.
fs
67kHz
B tB=15s ts
IDS
IDS C
Assume the resonant period is 2 s 1 15s 1 17 s 1 19 s 1 21s
tB=15s ts
59kHz 53kHz 48kHz
AVS trigger point
Constant frequency
Variable frequency within limited range DCM AVS region
IDS
IDS
CCM
tB=15s
D tW=6s
FSQ0765R Rev. 00
D
C
B
A
Vin
FSQ0765R Rev.00
ts
max=21s
Figure 42. QRC Operation with Limited Frequency
Figure 43. Switching Frequency Range
Vgate
Synchronize Synchronize
Vgate continued 2 pulses 1st valley switching fixed
Vgate continued another 2 pulses 2nd valley switching fixed fixed fixed
Vgate continued 2 pulses 1st valley switching fixed
GateX2 One-shot AVS
fixed triggering
1st or 2nd is depend on GateX2
de-triggering triggering
1st or 2nd is dependent on GateX2
VDS
tB
tB
tB
tB
tB
tB
GateX2: Counting Vgate every 2 pulses independent on other signals. FSQ0765R Rev. 00
1st valley- 2nd valley frequency modulation. Modulation frequency is approximately 17kHz.
Figure 44. Alternating Valley Switching (AVS)
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 16 www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
PCB Layout Guide
Due to the combined scheme, FPS shows better noise immunity than a conventional PWM controller and MOSFET discrete solution. Furthermore, internal drain current sense eliminates noise generation caused by a sensing resistor. There are some recommendations for PCB layout to enhance noise immunity and suppress the noise inevitable in power-handling components. There are typically two grounds in the conventional SMPS: power ground and signal ground. The power ground is the ground for primary input voltage and power, while the signal ground is the ground for PWM controller. In FPS, those two grounds share the same pin, GND. Normally the separate grounds do not share the same trace and meet only at one point, the GND pin. Moreover, wider patterns for both grounds decrease resistance for large currents. Capacitors at the VCC and FB pins should be as close as possible to the corresponding pins to avoid noise from the switching device. Sometimes Mylar(R) or ceramic capacitors with electrolytic for VCC are better for smooth operation. The ground of these capacitors needs to connect to the signal ground (not power ground). The cathode of the snubber diode should be close to the drain pin to minimize stray inductance. The Y-capacitor between primary and secondary should be directly connected to the power ground of DC link to maximize surge immunity. Because the voltage range of feedback and sync line is small, it is affected by the noise of the drain pin. Those traces should not draw across or close to the drain line. When the heat sink is connected to the ground, it should be connected to the power ground. If possible, avoid using jumper wires for power ground and drain.
Figure 45. Recommended PCB Layout
Mylar(R) is a registered trademark of DuPont Teijin Films.
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 17
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
Physical Dimensions
TO-220F-6L (Forming)
1 0 .16 9 .9 6 3 .4 0 3 .2 0 (7 .00) O 3 .2 8 3 .0 8
2 .7 4 2 .3 4 (0 .70 )
(5 .4 0 )
6 .9 0 6 .5 0
1 6 .07 1 5 .67
2 0 .0 0 1 9 .0 0
(1 3 .0 5 ) 2 4 .0 0 2 3 .0 0 R 0.55 (0 .4 8 )
8 .1 3 7 .1 3
R 0.55 1 .4 0 1 .2 0 (1 .1 3 )
1 6
0 .8 0 0 .7 0 0 .7 0 0 .5 0 1 .7 5 1 .2 7 3 .8 1
2 ,4 ,6 1 ,3 ,5
3 .0 6 2 .4 6 (7 .1 5)
2 .1 9
0 .6 0 0 .4 5 3 .4 8 2 .8 8
5
5
N O T E S : U N LE S S O T H E R W IS E S P E C IF IE D A ) T H IS P A C K A G E D O E S N O T C O M P LY T O A N Y C U R R E N T P A C K A G IN G S T A N D A R D . B ) A LL D IM E N S IO N S A R E IN M IL LIM E T E R S . C ) D IM E N S IO N S A R E E X C L U S IV E O F B U R R S , M O L D F L A S H , A N D T IE B A R E X T R U S IO N S . D ) L E A D F O R M O P T IO N A E ) D F A W IN G F IL E N A M E : T O 2 2 0 A 0 6 R E V 4
Figure 46. 6-Lead, TO-220 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 18
www.fairchildsemi.com
FSQ0765RS -- Green-Mode Fairchild Power Switch (FPSTM) for Quasi-Resonant Operation
(c) 2008 Fairchild Semiconductor Corporation FSQ0765RS * Rev. 1.0.2 19
www.fairchildsemi.com

▲Up To Search▲

Price & Availability of FSQ0765RS

	To Download FSQ0765RS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .